A Variability Tolerant System-on-Chip Ready Nano-CMOS Analog-to-Digital Converter

As integrated circuit technologies progress to nanoscale, process variations become relatively large and significantly impact circuit performance. The proactive management of process variation during the design process is critical to ensure effective device yield and to keep manufacturing costs down. In the present scenario, designers are searching for analog-to-digital converter (ADC) architectures which are nanoscale CMOS processes tolerant. Expectations on the performance of ADCs are continuously increasing along with the progress of digital systems. A process and supply variation tolerant, System-on-Chip (SoC) ready, 1GS/s, 6 bit flash ADC suitable for integration into nanoscale digital CMOS technologies is presented. The physical design of the ADC has been done using a generic 90nm Salicide 1.2V /2.5V 1 Poly 9 Metal process design kit. Baseline post layout simulation results at nominal supply and threshold voltages are presented. The parasitic-extracted physical design of the ADC is then subjected to a corner based methodology of process variation. The results show that process variation causes a maximum variation of 10.5% in the INL and 5.7% in the DNL, with both INL and DNL being less than 0.5LSB. The 90nm ADC consumes a peak power of 5.794mW and an average power of 3.875mW . The comparators for the ADC have been designed using the threshold inverting technique. To show technology scalability of the design, the ADC has also been presented using 45nm Predictive Technology Models (PTM). At 45nm, INL = 0.46LSB, DNL = 0.7LSB and a sampling rate of 100MS/s were obtained. The 45nm ADC consumes a peak power of 45.42μW , and average power of 8.8μW .